1. Field of the Invention
The invention relates to a circuit arrangement for controllably delaying electrical signals. A preferred but not exclusive field of application of the invention is the controllable delay of clock signals in digital circuits.
2. Description of the Related Art
Controllable delay circuits are known and commonly used which contain a chain of a plurality of delay elements each having fixed (and in most cases equal) transit time and have a selection device which is connected to taps off of the chain in order to select a respective required tap and by this means to insert a required part-section of the chain between the circuit input and circuit output. The effective total delay between input and output is then equal to the sum of the transit times of the delay elements located in the selected part-section. The selection device usually contains, for each of the selectable taps, a selectively closable switching link which leads from the relevant tap to a common connection. In many known embodiments, this common connection is the input of the circuit where the signal to be delayed is applied (feed multiplex). In other embodiments, the common connection is the output where the delayed signal is taken off (take-off multiplex). Embodiments with two outputs are also known in order to obtain from one input signal two controllably delayed signals which are shifted in time with respect to one another by a fixed measure. In this arrangement, two selection devices are provided which are allocated in an interleaved manner to alternating taps of the same chain (in the case of feed multiplex) or each of which is allocated to a separate chain of two chains operated in parallel (in the case of take-off multiplex).
All these conventional embodiments have certain disadvantages which will be explained in greater detail in the text which follows by means of FIGS. 1 to 4 of the attached drawings.
FIG. 1 shows a known delay circuit with feed multiplex and a single output.
FIG. 2 shows a known delay circuit with take-off multiplex and a single output.
FIG. 3 shows a known delay circuit with feed multiplex and two outputs.
FIG. 4 shows a known delay circuit with take-off multiplex and two outputs.
In all figures, identical or similar elements are provided with in each case identical reference symbols in capital letters which are followed by a number or a lower-case letter as running number for closer identification. In the description following, the lower-case letter “i” is used as representative of an “arbitrary” number.
The known embodiment of a delay circuit, shown in FIG. 1, contains a chain K of a multiplicity n of similar delay elements A1 to An which are directly connected in series and each of which is an active (that is to say non-passive) and unidirectional circuit with a defined fixed transit time (“elementary delay”) τE. In the example shown, n=6. The definitions “unidirectional” and “active” mean that the element transmits signals only in one direction and acts as driver, in such a manner that the signal level does not significantly decrease when passing through the chain from element to element. Accordingly, the delay elements A1 . . . An in FIG. 1 (and also the delay elements in all other figures) are represented by the usual driver symbol in the form of a triangle, the point of which marks the output. If the signal to be delayed is a binary signal such as, e.g., a clock signal or a digital signal, two (or a greater even number of) series-connected inverters are in each case preferably used as delay elements A1 . . . An.
The input connection X of the delay circuit according to FIG. 1 is at the input side of the chain K, that is to say at the input of the first delay element A1. The chain K has at the output of each of the elements A1 . . . An a tap which can be selectively connected to an output connection Y. For this purpose, a total of n switching links SA1 . . . SAn are provided, in each case one for each of the taps at the outputs of the elements A1 . . . An. Each of these switching links can be made to conduct (“switched through”) or blocked by an associated control signal. For the sake of illustration, the switching links are drawn symbolically like mechanical line switches. In reality, they are usually electronic switches, for example, in the form of field-effect transistors, preferably MOSFETs. In FIG. 1, a corresponding embodiment of the switch SA1 is shown in detail as representative of all switches SA1 . . . SAn which are all constructed in the same manner. The field-effect transistor FET shown forms the relevant switching link by means of the channel between the source diffusion region S and the drain diffusion region D. This link is blocked (non-conducting “0 state”) if a binary control signal (0 or 1) applied to the gate G of the FET has a binary value “0” and conducting (switched-through “1 state”) if the control signal has a binary value “1”.
To operate the delay circuit according to FIG. 1, only a single one of the n switching links SA1 . . . SAn is switched through, the total delay τY from the input connection X to the output connection Y being determined by the selection of the corresponding switching link. In general, it holds true for switching through the ith switching link SAi that the input signal passes through a number i of the delay elements (namely elements A1 . . . Ai) on its way from the input X to the output Y. In the ideal case, when the transit times via the respective connecting lines and switching links are negligibly small, the value i*τE is obtained for the total delay τY (the symbol * stands for the operator of the multiplication here and in the text which follows). In practice, however, the problems described below can occur.
A first problem involves the line delays which, in practice, are frequently not negligible and therefore can lead to noticeable inaccuracies in the adjustment of the delay circuit. The time constant of these delays is the effective resistance of the switching link in each case switched through multiplied by the electrical capacity of the line length between the associated tap of the chain K and the circuit output. Since the signal to be delayed passes through different line lengths at different multiplexer settings, which is hard to avoid in the circuit arrangement according to FIG. 1, the contribution of the line delay to the total delay τY differs from setting to setting. Thus, the total delay does not change linearly with the number of delay elements traversed from X to Y, i.e. the control characteristic (τY as a function of i) is nonlinear which is undesirable for many applications. To produce linearity, the delay circuit must be aligned with great effort, for example by means of different trimming of the transit times of the various delay elements A1 . . . An within the chain K or by inserting and trimming additional delay elements in the line system. This can only be done by means of measurements on the completed delay circuit.
A second problem is the total load which must be driven by the associated delay element Ai via the switching link SAi switched through in each case. Apart from the external output load at the output connection Y, this total load contains a number of internal load components, namely, firstly, the input impedance of the delay element Ai+1 following, secondly the parasitic capacitances of the switching link SAi switched through, thirdly the electrical capacity of the entire line system between the switching links SA1 . . . SAn and the output connection Y and fourthly all parasitic capacitances which are effective at the ends of all other switching links (not switched through) connected to this line system. When field-effect transistors are used, the above-mentioned parasitic switch capacitances are mainly the capacitance CSB between source diffusion region S and bulk B (substrate) and the capacitance CDB between drain diffusion region D and bulk B. These capacitances are drawn in at the FET shown in FIG. 1.
Naturally, the total load described increases with the length of the delay chain K, i.e. with the number n of delay elements. At some point, the load becomes too great for an individual delay element Ai so that the maximum chain length must be limited. This is of disadvantage because, as a result, the maximum delay which can be set is restricted. One way out is to subdivide the chain into a number of sections, each of which operates into a separate multiplexer which are then brought together in a tree circuit, in each case by interposing an amplifier via one or more further multiplexer levels. Apart from the high circuit expenditure, this stepped multiplexing has the further disadvantage that the stepping itself introduces additional line delay which has the result that the minimum value of the adjustable delay is relatively great. Furthermore, this additional delay is not a linear function of the number of delay elements traversed. This additionally increases the above-mentioned adjustment effort for linearizing the control characteristic.
Similar problems arise if the delay circuit is designed for operation with feed multiplex as shown in FIG. 2. In this arrangement, before each delay element Ai in the delay chain K, a switch SAi is provided which can be selectively operated in order to connect the input of the relevant delay element to the input connection X. When such a connection is established, the output of the preceding delay element A(i−1) in the chain should be effectively decoupled from the input connection X. This can be achieved, for example, by constructing the switches as change-over switches (2:1 multiplexers) as is illustrated by corresponding switch symbols in FIG. 2. Each switch SAi can be switched between two states by a binary control signal (0/1) in order to connect the input of the relevant delay element Ai either to the input connection X via a connection “1” (“1 state” of the switch) or in order to connect the input of the relevant delay element Ai to the output of the preceding delay element A(i−1) via a connection “0” (“0 state” of the switch). The “0” connection of the switch SA1 preceding the first delay element A1 remains unused.
The switches SA1 . . . SAn in the delay circuit according to FIG. 2 also have parasitic capacitances which are effective at their connections. These switches can also be formed by FETs as is shown in detail for the switch SA2 in FIG. 2 as representative of all switches SA1 . . . SAn which are all constructed in the same manner. The channel of a field-effect transistor FET1 forms the switching link from the “1” connection to the input of the subsequent delay element and is switched through when a binary control signal has the binary value “1”. The channel of a field-effect transistor FET0 forms the switching link from the “0” connection to the input of the subsequent delay element and is switched through when a binary control signal has the binary value “0”.
In the operation of the circuit according to FIG. 2, only a single one of the switches SA1 . . . SAn is set into the 1 state. The signal to be delayed then passes from the input connection X to the input of the associated delay element and then passes through the rest of the chain K to the output connection Y which is located at the output of the last delay element An and where the signal can be taken off with a delay of (n−i+1)*τE.
The input signal must here work into a load which is composed of the sum of the parasitic capacitances at the “1” connections of the switches SA1 . . . SAn and the impedance of the entire line system between the input connection X and these switches. As the chain is very long, this requires a driver with enormous power. In many environments, such a driver is not practicable so that, in practice, the maximum length of the chain must be limited. With regard to the line delays, the same problems arise as in the circuit arrangement according to FIG. 1.
As has already been indicated, it is also known to extend controllable delay circuits of the type described above in such a manner that two versions of the input signal displaced with respect to one another by a fixed time scale can be taken off at two output connections, namely an “early” version of controllable delay time and a “late” version which appears later than the early version by the fixed time scale τE. Such delay circuits are used in, among other things, DLL (delay locked loops), particularly for regulating the time displacement of a binary clock signal. Such a clock signal usually consists of a pulse sequence, the rising or falling edges of which in each case determine the clock cycle when a predetermined threshold value is reached. By means of weighted superimposition of the late version of a clock edge, delayed by τE, on the early version of this edge in a suitable mixer, a resultant clock edge can be obtained which reaches the threshold value at a time within the time interval between early and late version, this time being controllable by controlling the relative weighting in the mixer.
FIG. 3 shows a first known embodiment of a controllable delay circuit for supplying the above-mentioned early and late versions of a clock signal at the input end. This circuit operates with take-off multiplex and differs from the circuit according to FIG. 1 in that, instead of a single output connection Y, two output connections Ya and Yb are provided. The taps of the delay chain K at the outputs of each second delay element A2, A4, . . . (all even-numbered elements) lead to the second output connection Yb via associated switching links SAb1, SAb2, . . . and the taps at the outputs of the other delay elements A1, A3, . . . (all odd-numbered elements) lead to the output connection Ya via associated switching links SAa1, SAa2, . . . . Selective switching-through of, in each case, one pair of switches SAai, SAbi has the result that the clock signal applied at the input connection X appears as “late” clock with a delay of 2i*τE at the output connection Yb and as “early” clock with a delay of (2i−1)*τE, less by τE, at the output connection Ya.
FIG. 4 shows an alternative known embodiment of a controllable delay circuit for supplying early and late versions of a clock signal at the input end. This circuit operates with feed multiplex similar to the circuit of FIG. 2 but contains two delay chains Ka and Kb, each of which leads to a separate output connection Ya and Yb, respectively. The chain Kb contains n delay elements B1 . . . Bn, the inputs of the elements B1, B3, . . . (that is to say all odd-numbered elements) being selectively connectable to the input connection X via associated switches SB1, SB2, . . . . The chain Ka contains n−1 delay elements A1 . . . A(n−1), the inputs of the elements A1, A3, . . . (that is to say all odd-numbered elements) being selectively connectable to the input connection X via associated switches SA1, SA2, . . . . The selective switching of in each case one pair of switches SBi, SAi into the 1 state has the result that the clock signal applied at input connection X appears as “late” clock with a delay (n−2i+2)*τE at the output connection Yb and as “early” clock with a delay (n−2i+1)*τE, less by 1τE, at the output connection Ya.
In the known early/late delay circuits according to FIGS. 3 and 4, the same results are obtained as have been described above for the known circuits according to FIGS. 1 and 2. That is to say, in the conventional art, the loads on individual circuit sections and also the inaccuracies of the delays set in each case increase with the length of the delay chains. In the variant of FIG. 4, an additional further disadvantage is that a relatively large number of delay elements is needed; a control range of the delay from 1τE to n*τE requires a total of 2*n−1 delay elements.
Therefore, there is a demand for a controllable delay circuit operating with tapped delay chain, in such a manner that the maximum load on the circuit elements needed for the operation is less than in the conventional art and independent of the chain length.